From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the technology, while lookup tables (LUT) resulting from a physics model have applied TFET. To consider parasitic effects circuit performances, nm-based circuits laid out, included in TFET LUT implementation. post-layout simulations, including parasitic, demonstrate conventional CCDD that technology larger dynamic range (DR) (>60%) and better 1 V-sensitivity than planar has. Note that, case, figure of merit defined by Voltage Conversion Efficiency (VCE) Power (PCE) remains somewhat similar. On other hand, topology proposing VCE at cost low PCE shows lower performance expected reported data nodes (e.g., 180 nm). The TFET-based 70%, 82% with an 8 dB DR (>60%), best work. Because low-bias condition good reverse current blocking (unidirectional channel), offers new perspectives RF-DC rectifier/multiplier topology, which usually limited